Realization of Asynchronous Null Convention Logic Circuits using Mapping Algorithm

Shraddha Bhardwaj; Riyaj Kazi

CALL FOR PAPERS : Oct-2023

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25-Oct-23

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Realization of Asynchronous Null Convention Logic Circuits using Mapping Algorithm

Author(s):

Shraddha Bhardwaj , Dr.D.Y. Patil School Of Engineering , Pune; Riyaj Kazi, Dr.D.Y. Patil School Of Engineering , Pune

Keywords:

Automation, Gate Mapping, NULL Convention Logic, Technology Mapping

Abstract:

Designs with higher performances, more complexity and shrinking feature size increases the prevalence of asynchronous design paradigms in the multi-billion dollar semiconductor industry. The automation techniques therefore become a challenge in the application areas of asynchronous circuits. In this paper a new methodology is suggested which is used for mapping multi-rail logic expressions to NCL Gate Library. This methodology is then compared to a method which already exists. These methods are implemented in VHDL programming language. The outcome is increased performance in terms of delay and area.